1. Introduction
In a paging system, programs generate logical addresses, but memory hardware requires physical addresses. Therefore, every memory reference must be translated before actual memory access occurs.
This conversion of a logical address into a physical address is called Address Translation.
Address translation is performed by the Memory Management Unit (MMU) using information stored in the Page Table.
2. Logical Address Format
In paging, a logical address is divided into two fields:
Logical Address = Page Number (p) + Offset (d)
Components
Page Number (p)
Identifies the page to which the address belongs.
Offset (d)
Identifies the exact location within that page.
Example
Logical Address = (p = 2, d = 100)
Here:
Page Number = 2
Offset = 100
3. Physical Address Format
After translation, the physical address is represented as:
Physical Address = Frame Number (f) + Offset (d)
Key Observation
The offset remains unchanged during translation.
Only the page number is replaced by the corresponding frame number.
Page Number → Frame Number
Offset → Same Offset
4. Role of the MMU
The Memory Management Unit (MMU) is dedicated hardware responsible for translating logical addresses into physical addresses.
Functions of MMU
Extract page number
Access page table
Obtain frame number
Generate physical address
Enforce memory protection
Translation Flow
CPU
↓
Logical Address
↓
MMU
↓
Page Table Lookup
↓
Frame Number
↓
Physical Address
↓
RAM
5. Address Translation Procedure
The translation process follows four steps.
Step 1: CPU Generates Logical Address
Example:
(Page 2, Offset 100)
Step 2: Extract Page Number
Page Number = 2
Step 3: Consult Page Table
Suppose:
| Page | Frame |
|---|---|
| 0 | 5 |
| 1 | 2 |
| 2 | 8 |
| 3 | 1 |
From the page table:
Page 2 → Frame 8
Step 4: Generate Physical Address
Replace page number with frame number.
(Frame 8, Offset 100)
This becomes the final physical address.
6. Address Translation Formula
The physical address can be computed using:
Physical Address
=
(Frame Number × Page Size)
+
Offset
This is the most important formula in paging numericals.
7. Numerical Example
Given
Page Size = 1 KB = 1024 Bytes
Logical Address = 2050
Page Table:
| Page | Frame |
|---|---|
| 0 | 5 |
| 1 | 2 |
| 2 | 8 |
Step 1: Find Page Number
Page Number
=
2050 ÷ 1024
=
2
Step 2: Find Offset
Offset
=
2050 mod 1024
=
2
Logical Address:
(Page 2, Offset 2)
Step 3: Find Frame Number
From page table:
Page 2 → Frame 8
Step 4: Calculate Physical Address
Physical Address
=
(8 × 1024) + 2
=
8194
Final Answer
Physical Address = 8194
8. Another Numerical Example
Given
Page Size = 512 Bytes
Logical Address = 1300
Page Table:
| Page | Frame |
|---|---|
| 0 | 3 |
| 1 | 7 |
| 2 | 4 |
Step 1: Page Number
1300 ÷ 512
=
2
Step 2: Offset
1300 mod 512
=
276
Logical Address:
(Page 2, Offset 276)
Step 3: Frame Number
Page 2 → Frame 4
Step 4: Physical Address
(4 × 512) + 276
=
2324
Final Answer
Physical Address = 2324
9. Bit-Level Understanding
For exams, page sizes are often powers of two.
If:
Page Size = 2ⁿ
Then:
Offset = n bits
The remaining bits represent the page number.
10. Example: Bit Division
Suppose:
Logical Address = 16 bits
Page Size = 4 KB
Since:
4 KB = 4096 Bytes = 2¹²
Offset requires:
12 bits
Therefore:
Page Number Bits
=
16 − 12
=
4 bits
Address Structure
| Page Number | Offset |
|----4 bits---|--12 bits--|
11. Example: 32-bit Address Space
Suppose:
Logical Address = 32 bits
Page Size = 4 KB = 2¹²
Then:
Offset = 12 bits
Page Number:
32 − 12
=
20 bits
Address Structure:
| Page Number | Offset |
|---20 bits---|12 bits|
Number of Pages:
2²⁰
=
1,048,576 pages
12. Address Translation Flow Diagram
CPU
↓
Logical Address
(Page Number, Offset)
↓
MMU
↓
Page Table
↓
Frame Number
↓
(Frame Number, Offset)
↓
Physical Address
↓
Main Memory
13. Performance Issue in Paging
A major drawback of paging is the extra lookup required.
Without paging:
CPU
↓
Memory Access
Only one memory access is required.
With paging:
CPU
↓
Page Table Access
↓
Memory Access
Two memory accesses are required.
14. Effective Memory Access
Without TLB:
1 memory reference
=
2 memory accesses
Example:
Memory Access Time = 100 ns
Then:
Total Time
=
100 + 100
=
200 ns
Performance decreases significantly.
15. Solution: Translation Lookaside Buffer (TLB)
To reduce translation overhead, modern systems use a Translation Lookaside Buffer (TLB).
A TLB is a small, high-speed cache that stores recently used page table entries.
Working
CPU
↓
TLB Lookup
↓
Hit ? -------- Yes → Frame Number
↓ No
Page Table Lookup
↓
Frame Number
↓
Physical Address
Benefits
Faster address translation
Reduced memory accesses
Improved performance
16. TLB Hit and TLB Miss
TLB Hit
Required page table entry is already in the TLB.
TLB → Frame Number
Only one memory access is needed.
TLB Miss
Entry not found.
TLB
↓
Page Table
↓
Memory
Extra lookup required.
17. Key Insights
Page Number Changes
Page Number → Frame Number
Offset Never Changes
Offset → Same Offset
MMU Performs Translation
Logical Address
↓
MMU
↓
Physical Address
Core Formula
Physical Address
=
(Frame Number × Page Size)
+
Offset
Paging Cost
Extra page table lookup
Solution
TLB
18. Exam-Oriented Summary
Logical Address
Page Number + Offset
Physical Address
Frame Number + Offset
Translation Steps
Extract page number
Access page table
Obtain frame number
Combine with offset
Formula
Physical Address
=
(Frame Number × Page Size)
+
Offset
Important Point
The offset remains unchanged during translation.
Performance Problem
Two memory accesses per reference
Performance Solution
Translation Lookaside Buffer (TLB)
Most Important Statement
Address translation is the process by which the MMU converts a logical address generated by the CPU into a physical address using the page table, enabling processes to execute independently of their actual memory locations.